생성형 AI의 급속한 발전으로 고성능 컴퓨팅(HPC)에 대한 수요가 크게 증가하였고, 다양한 컴퓨팅 환경에 최적화된 디자인 인프라의 중요성이 더욱 강조되고 있습니다. 이에 삼성 파운드리는 각 제품 요구 특성에 맞춰  맞춤형 HPC/AI 플랫폼과 Automotive 플랫폼을 제공하고 있고, DTCO(Design-Technology Co-optimization)기술을 적극 활용하여 제품 성능(Power, Performance, Area)을 향상 시키고 있습니다. 고성능/저전력 성능 최적화를 위한 대표적인 DTCO 항목으로는 Hyper cell, Fusion cell 등이 있으며, Cadence와의 협력을 통해 이러한 기술들을 고객 제품에 효과적으로 적용하였습니다.

As the AI industry is rapidly shifting its focus from AI Training to AI Inference, memory technologies must evolve to support high-performance and power-efficient token generation across Generative, Agent and Physical AI. Performance and power efficiency remain two critical pillars shaping the scalability and TCO of AI systems. To address these demands, SK hynix delivers a comprehensive memory portfolio-spanning HBM, DRAM, compute SSDs, and storage SSDs optimized for diverse AI environments including data centers, PCs, and smartphones. HBM, with its structural advantages of high bandwidth and low power consumption, provides the flexibility to meet a wide variety of customer needs. Meanwhile, our storage solutions are designed to enable fast, reliable access to data-intensive workloads in AI inference scenarios. Together, these efforts form a mid-to-long-term roadmap focused on scalability, performance, and cost optimization. This keynote will highlight how SK hynix’s memory technologies are enabling the infrastructure required for next-generation AI.

System-Technology Co-Optimization (STCO) has become an critical paradigm in the semiconductor industry with the emergence of advanced packaging technologies, which integrate multiple dies, interposers, and substrates to meet the performance and power requirements of the AI era. However, applying STCO to advanced packaging designs presents significant challenges due to the fundamental differences between silicon-based chip fabrication and organic material-based packaging manufacturing.

This complexity extends to the system design side, where integration requires a diverse suite of electronic design automation (EDA) solutions, including tools for system planning, silicon die place-and-route, and package design for RDL interposers and substrates. Even after the implementation stage, additional EDA software is required for electrical, thermal, and mechanical simulation to complete system-level sign-off.

To mitigate these design complexities, we have established a flow based on Cadence Integrity 3D-IC platform for our I-CubeE 2.3D advanced packaging technology and validated it through case studies. In this presentation, we will discuss how the entire system planning, implementation, and system-level verification processes for I-CubeE designs can be seamlessly executed. We will also show how the power/ground bumps and power delivery networks can be optimized in the early design stage using the Integrity 3D-IC platform.

This is an update on digital tools and AI capabilities that can improve designer productivity and achieve better silicon power, performance, and area. This presentation will cover the full Cadence RTL-GDS implementation, signoff, and 3D-IC design flow.

As the power efficiency of semiconductors becomes increasingly important, the demands of device scaling is very powerful. However, due to physical constraints caused by device scaling, the channel width of extreme high density (xHD) cell decreases, resulting in a decrease in cell speed and drivability. This problem not only weakens the maximum chip performance but also reduces power efficiency. In this paper, we introduce a design methodology using hyper cell that merges adjacent channels to solve the problem of speed degradation due to device scaling. The hyper cell has place and route (P&R) constraints to prevent a process risk caused by the merged channel. We introduce P&R strategies to minimize the physical overheads from the P&R constraints and maximize the performance gain of hyper cells.

With increasing demands for MIMCAP solutions, Cadence and Samsung Foundry have collaborated to develop an advanced MIMCAP solution, leveraging the strengths of both companies to drive innovation in high-performance products. This strategic partnership has resulted in the creation of a comprehensive MIMCAP insertion methodology utilizing Cadence's Innovus and Pegasus systems, leading to significant improvements in runtime, density, and post-processing techniques. The outcome of this collaboration is expected to enhance chip design solutions and meet the growing demands for high-performance products.

As design teams implement and signoff the most challenging designs across a wide range of foundry process nodes, the Cadence Digital full flow is continually improving to enable the best power and performance results for ever larger and complex system on chips (SoC). This session contains in-design solutions with Pegasus features.

As technology nodes scale down to 4nm and beyond, ensuring robust operation of AI and high-performance computing designs at lower voltages without sacrificing frequency is essential for power efficiency. Traditional static timing analysis (STA) often relies on worst-case assumptions, leading to conservative margins that limit voltage scaling. This presentation introduces an enhanced STA methodology built using Samsung’s process development kit (PDK) that combines voltage-aware path profiling, adaptive delay modeling, and slack budgeting. Without incurring additional runtime overhead, it enables accurate timing analysis at reduced voltages, improving power efficiency and resilience to process variations, especially for AI accelerators and low-power SoCs. To further strengthen timing robustness, the methodology incorporates Tempus Parameterized Timing Robustness (PTR), which uses statistical analysis to compute the probability of all paths meeting timing across varying PVT conditions. By modeling delay variations and correlations, PTR provides a more realistic assessment than worst-case analysis, enabling designers to quantify timing risks and make informed trade-offs. Integrated into the ECO flow, PTR also helps identify and optimize high-variation bottlenecks early, improving convergence. Validated through SPICE correlation, this approach enhances reliability, reduces pessimism, and accelerates timing closure.

This abstract presents an advanced methodology for power integrity (PI) analysis in 3D-IC integration, a crucial component in achieving higher performance, power efficiency, and system scalability in modern semiconductor technology. As the complexity of power delivery networks (PDNs) in 3D-IC architectures increases, challenges such as IR drop, electromigration (EM), and simultaneous switching noise (SSN) necessitate effective management to ensure reliable operation. Traditional 2D-IC PI techniques often fall short in addressing the vertical interactions and multi-die dependencies characteristic of 3D-IC designs.

We propose a comprehensive methodology for full-flow power integrity analysis, encompassing the entire design process from early exploration to final sign-off, employing Cadence's advanced EDA tools, including Voltus, Innovus, and Integrity 3D-IC. This innovative approach utilizes adaptive partitioning techniques, hierarchical modeling, and macro abstraction methods to enhance simulation accuracy and reduce the turnaround time (TAT) for electromigration and IR (EMIR) analysis.

Adaptive Partitioning for Efficient 3D-IC Simulation:

•    Die-to-Die Stack Consideration: Tackles the challenge of managing a vast number of inter-die bumps by optimizing bump mapping relationships.

•    Bump Mapping Relation: Accurately calculates die-to-die locations for improved spatial alignment.

•    Partitioning Strategy: Groups dies with similar spatial areas into the same partition, effectively minimizing unnecessary iterations during simulation.

•    Simulation Efficiency: Reduces computational overhead while enhancing the convergence speed of power integrity analysis.

XM-Based Hierarchical Modeling for Efficient 3D-IC EMIR Analysis:

•    High-Accuracy Macro Modeling: XM enables the creation of compact, reduced-order macro-models for individual blocks, dies, or chiplets.

•    Capturing Essential PDN Characteristics: The models effectively capture critical RC and dynamic behaviors while mitigating computational overhead.

•    Hierarchical Integration: Facilitates the efficient integration of block-level models into full-chip or system-level EMIR analysis without the need for re-simulation.

•    Scalability for Complex 3D-ICs: Supports large-scale designs featuring multiple dies and interconnect levels, significantly improving analysis speed and accuracy.

A case study of adaptive partitioning applied to Samsung Foundry's 2.5D advanced node design, which incorporates 100K bumps, achieves over a 10% reduction in EMIR simulation turnaround time with less than 5% accuracy loss. Additionally, another case study of XM-Based Hierarchical Modeling on Samsung Foundry's advanced node design illustrates remarkable efficiency, achieving over a 50% reduction in EMIR simulation turnaround time with less than 1% accuracy loss without package considerations and a 5% accuracy loss with package inclusion. Notably, the number of Power/Ground (PG) node counts to solve decreases from 5.8 billion in the flat case to 2.6 billion. By implementing this full-flow methodology, designers can significantly enhance PI closure for complex 3D-IC designs, ensuring robust, manufacturable, and high-performance semiconductor solutions. This abstract provides a detailed overview of the proposed strategies, paving the way for optimized power integrity sign-off in next-generation 3D-IC architectures.

Chiplet 기술은 요즘 반도체 trend 중 가장 popular 한 분야입니다. 특히 HPC 성능이 요구되는 server향 SoC의 경우 HBM이 사용됨에 따라, chiplet design은 필수 사항이 되었습니다. chiplet design은 chiplet 사이의 fine pitch routing 연결을 위한 Si-interposer, Si-bridge과 같은 interconnection 설계와 해당 interconnector와 각 chiplet(SoC/HBM)을 조립하는 Package 설계가 필요합니다. Si-interposer, Si-bridge는 같은 interconnector의 설계는 silicon 기술을 활용하다 보니 기존 SoC 설계를 하던 PD engineer가 설계하는 반면, 해당 설계를 위한 floorplan/netlist와 같은 input을 제공하는 쪽은 Pacakge 설계자 입니다. 하지만 Package 설계자가 사용하는 netlist 등의 interface format은 SoC designer들이 사용하는 format과 달라 I/F에 많은 어려움이 있었습니다. 본 과제에서는 Cadence에서 제공하는 Integrity 3DIC를 활용해 그러한 wall을 극복할 수 있었고, INNOVUS에서 제공하는 RDL routing 기능으로 si-interposer를 설계할 수 있었습니다.

This presentation covers how various companies in the EDA and Systems space are accelerating their chip design by leveraging Cadence tools in the cloud, from front-end to back-end workflows including emulation in the Cloud. Many companies from start-ups to large companies globally are accelerating innovation, engineering productivity and time to tape out using the scalability and flexibility offered by the Cloud, and this presentation will cover some examples from the industry. We’ll also cover the current advances and challenges for cloud migration including aspects of security in the cloud. Finally, the presentation will touch upon how customers can take advantage of the latest AI/ML enabled Cadence tools in the cloud and how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. You’ll learn how to harness the full potential of cloud technology to streamline your EDA workflows and accelerate innovation. 

As the size and complexity of memory circuits have increased, Fast SPICE simulator has become a key tool in Memory design.

Circuit detection and partitioning are the core technologies in Fast SPICE simulation that aim to reduce simulation time while maintaining target accuracy.

This paper presents how we improved simulation time for SK hynix’s Memory designs through the application of circuit detection and partitioning techniques of Spectre FX.

Samsung Electronics SLSI Business Division DT Team and Cadence Korea Virtuoso Team worked closely together to implement several effective new design features within Virtuoso for high-performance, low-power and small-area Custom SRAM physical designs. These features are helping Samsung develop cache memory with optimal PPA in its latest process, and contributing to use in the latest products by reducing SRAM design TATs. Furthermore, this collaboration model has the next plan to ultimately develop a framework for SRAM periphery DTCO through these features. In this session, the concepts, effects and practical use cases of these features including Device level APR, Layout Conversion and SRAM DM Assistant are explained and our future plans utilizing them are introduced.

As the semiconductor manufacturing process becomes more refined, the difficulty of designing for fine processes increases. As a result, various verification methods have been proposed, and the time required for verification is also increasing. In this situation, reusing existing blocks or IPs has become an important part for faster design closure with minimum effort.  We present the results of performing the analog schematic migration flow including schematic porting, optimization, and verification through Cadence Virtuoso Studio. The entire flow has been validated by experimental results on Samsung Foundry Fin-FET technology.

Chip designers on advanced nodes meet stringent performance and area requirements while minimizing power. Furthermore, the market requires an aggressive time-to-market schedule with minimal design iterations. To fulfill these requirements, engineers need extensive simulation and huge computing resources. The Spectre Simulation Platform can provide various practical solutions, including AI solutions, to help chip designers overcome such challenges.

RF designs based on heterogeneous integration combine different technologies and materials, such as silicon, gallium arsenide (GaAs), and indium phosphide (InP), within a single module to optimize performance and functionality. To support RF multi-chip module development, the Virtuoso Heterogeneous Integration (Virtuoso HI) for RF solution incorporates new co-design capabilities for simultaneous editing of the IC and SiP modules, in-design electromagnetic (EM) analysis with multiple solvers to give designers different methods of physical extraction, and system-level DRC to support multi-technology layouts. In addition, Cadence has recently introduced the new Virtuoso Studio RF platform to support silicon MMIC design and RFIC/module co-design with a concurrent electrical/physical layout workflow required for RF to mmWave IP development. This talk presents how the Virtuoso HI solution and Virtuoso Studio RF platform work together to reduce the turnaround time for developing RF multi-chip heterogeneous modules.

Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips at the lowest costs. Efficient design for yield is a key capability of a design team that meets time-to-market requirements and is cost-effective.

When designing analog/mixed-signal, RF and digital full custom IP, designers must consider many influence factors and effects, such as temperature and supply voltage variation, on-chip variation and process variation in the manufacturing process.

Besides creating a circuit topology, full custom design engineers must calculate device parameters such as MOS geometries and resistor values, also commonly called sizing the circuit.  Sizing circuits to meet specs at all process corners and operating conditions while simultaneously minimizing power consumption and/or area has become a major challenge in full custom design, that many circuit designers struggle with on a daily basis.In this presentation we will discuss the full custom sizing workflow, addressing

•    Balancing difficult spec trade-offs at every PVT corner

•    Machine learning/AI and iterative optimization vs the random spice monkey

•    Optimizing for low power and small area with high parametric yield

•    Saving designers’ effort and reducing runtime by efficient automation

As analog design complexity continues to grow with each new technology node, traditional manual layout methodologies are becoming a significant bottleneck to achieving faster time-to-market. The shrinking of technology nodes also demands early parasitic awareness during the design phase, making layout prototyping a critical part of the flow.

Cadence’s Virtuoso Animate, part of the AI-driven layout prototyping solution in Virtuoso Studio, addresses these challenges by enabling rapid, reusable, and intelligent analog layout generation. Animate allows circuit designers to quickly create multiple layout prototypes with minimal manual effort. These prototypes can be extracted and simulated early to assess layout feasibility, parasitic effects, area consumption, and performance trade-offs.

By providing high-quality layout options upfront, Animate helps designers avoid multiple design iterations, improves productivity, and offers a better starting point for custom layout. This presentation explores how Animate transforms the analog layout process, empowering designers to focus more on innovation and less on manual rework.

This presentation covers how various companies in the EDA and Systems space are accelerating their chip design by leveraging Cadence tools in the cloud, from front-end to back-end workflows including emulation in the Cloud. Many companies from start-ups to large companies globally are accelerating innovation, engineering productivity and time to tape out using the scalability and flexibility offered by the Cloud, and this presentation will cover some examples from the industry. We’ll also cover the current advances and challenges for cloud migration including aspects of security in the cloud. Finally, the presentation will touch upon how customers can take advantage of the latest AI/ML enabled Cadence tools in the cloud and how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. You’ll learn how to harness the full potential of cloud technology to streamline your EDA workflows and accelerate innovation. 

State-of-the-art SoC verification utilizes a scalable and flexible Universal Verification Methodology (UVM) testbench that reflects the constrained random simulation techniques that generate massive random transactions, and a huge functional coverage model that ensures a thorough verification. Consequently, it takes the design verification team an enormous amount of time and resources to achieve functional coverage closure by repeatedly running simulations after manually changing constraints in the testbench to target uncovered areas.

SimAI Input Bias is a new methodology to effectively reduce the time and cost for functional coverage closure in SoC verification by leveraging artificial intelligence and machine learning techniques in an iterative flow that automatically adjusts targets and guides the simulation to reach a multitude of targets efficiently.

How to validate SoC performance in complex SoC design using Palladium emulator. Especially, Explain STB flow with easy bring up and test using existing emulation ported design. And enable to check data integrity under stress scenario of SoC behavior with DC-flow.

As semiconductor designs become increasingly complex and time-to-market shrinks, early verification and software development have become critical to project success. In this constantly evolving environment, prototyping serves as a strategic bridge between functional verification, RTL development, and system-level implementation.

The Cadence Protium X3 Enterprise Prototyping Platform is designed to meet these demands. Based on the Xilinx VP1902 Versal Premium device, this high-performance prototyping platform empowers design teams to achieve rapid development, scalable capacity, and faster software verification.

The Protium X3 platform delivers improved compilation speed and design capacity.

Furthermore, the Protium X3 and Palladium platforms work together dynamically to provide a unified verification environment that seamlessly transitions from emulation to prototyping without major modifications. The Protium X3 redefines the prototyping stage from a bottleneck to a steppingstone to first-silicon success.

This sessionn introduces; the key benefits of the Protium X3 platform.

This presentation shares our experience in significantly accelerating hardware verification using the Cadence Palladium platform. By applying model optimization techniques and parallel processing to both compile and run phases, we achieved a reduction in overall verification time. These improvements enhanced verification throughput and enabled early bug detection and faster design iterations. The session will focus on the key techniques applied and the measurable performance improvements achieved.

Application-level power visibility early in the design cycle is essential to designing energy efficient chips and meeting power targets. Palladium Dynamic Power Analysis (DPA) offers novel technologies to estimate power of real-world scenarios spanning billions of cycles for billion gates designs in hours. Palladium’s fast dynamic power analysis enables identification of power-hotspots in the design and provides insights into power efficiency of software-hardware interaction.

This presentation will share challenges associated with estimating power for real application workloads and how next generation of Palladium DPA innovation has accelerated SoC power estimation while providing a higher level of accuracy in pre-silicon environment. The presentation will also share how Palladium users have improved methodologies for IR drop analysis using DPA, enabling power integrity sign-off for real worst case power scenarios.

Generative AI is transforming how we interact with tools, enabling more intuitive, natural language-driven workflows that enhance productivity and simplify complex tasks. Cadence is advancing its efforts in Agentic AI technologies and developing solutions across its entire software portfolio. One of them is the Verisium SpecMiner, which accelerates design verification using advances in large language models to process natural language specifications. This includes translating natural language into SVAs and extracting testable items from sections of a spec to form a vPlan. We plan to generate whole testbenches and formal environments from the spec, with chat-based user interaction to fill in the gaps in the spec.

Power-aware verification using UPF is a key challenge in SoC projects, complicated by traditional emulators supporting only 2-state logic (‘0’, ‘1’). Cadence's Palladium Z2 enables practical 4-state emulation with native support for "X" and "Z", improving detection of power intent bugs like isolation and retention failures. This approach maintains the same compile and runtime model as 2-state emulation but requires more resources. It delivers up to 115× faster runtime than simulation, simplifying debugging and enhancing verification quality in real mobile-AP SoC designs.

This presentation addresses the performance challenges in HPC systems with multi-die architectures. We explore coherency protocols, inter-die communication overhead, and their impact on system efficiency. We also introduce the Cadence System VIP solution to identify bottlenecks and validate functionality for real HPC design.

This presentation covers how various companies in EDA and Systems space are accelerating their chip design by leveraging Cadence tools in the cloud - from front-end to back-end workflows including emulation in the cloud. Many companies from start-ups to large companies globally are accelerating innovation, engineering productivity and time to tape-out by using scalability and flexibility offered by Cloud and this presentation will cover some of the examples from the industry. We’ll also cover the current advances and challenges for cloud migration including aspects of security in the cloud. Finally, the presentation will touch upon how customers can take advantage of the latest AI/ML enabled Cadence tools in the cloud and how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. You’ll learn how to harness the full potential of cloud technology to streamline your EDA workflows and accelerate innovation. 

With the increasing complexity and integration of semiconductor technologies, reducing turnaround time (TAT) has become a critical factor in enhancing competitiveness in System-in-Package (SiP) development. Traditional design and simulation processes often suffer from extended TAT due to increased design iterations driven by higher integration density.

In this presentation, we propose a methodology that quantifies target specifications from the early design stage and adopts a concurrent design-analysis approach. By leveraging Cadence Allegro Package Designer and Sigrity tools, we minimized TAT and realized a highly efficient "1-shot 1-qual" design cycle that dramatically reduces iteration loops.

This improved design flow not only streamlines the SiP development process but also aligns perfectly with the requirements of advanced packaging solutions for Wide I/O and high-speed applications making it a core design methodology at CoAsia.

The HBM interface design on silicon interposer has very high density. When analyzing the designs, modeling considering TAT and accuracy is important. I will describe a case study of developing HBM3/3e design on silicon interposer using the Cadence Clarity tool. And I will describe a case study comparing the consistency between wafer measurements and Clarity.

High-density packaging such as HBM(High Bandwidth Memory) poses growing challenges in managing mechanical stress and warpage. This session presents an advanced mechanical simulation flow for HBM packages using Celsius Studio within the Integrity 3DIC platform. By integrating Celsius3D, even non-experts such as circuit designers can easily assess mechanical behaviors like warpage and stress without deep domain knowledge. The proposed methodology is especially effective for 2.5D/3D package engineers who need detailed and trustworthy warpage analysis.

Cadence SPB 25.1 is making waves with new levels of productivity and shift-left enabling features unlocked in our new release.  

In this session, both new and experienced designers will find many new features and performance improvements across the board. Table-Driven design (TDD), more integrated analysis flows, and a new unified PCB design cockpit each aim to improve inter- and intra-tool workflows. In addition to traditional design methodologies, this session will also introduce Allegro X AI and ASR solutions in SPB 25.1, which empower engineers to interact with their designs in new ways, explore alternate solutions, and solve parallel tasks with the power of cloud compute, or from on-prem deployments. Finally, as every project consumes more data, we will cover new Allegro X Pulse features for managing design data and team collaboration.

In the rapidly changing landscape of electronic design and optimization, the need for high computational capacity has become essential. The Clarity 3D Solver system is designed to meet this need by offering exceptional computational power and efficiency. This presentation will showcase the ability of Clarity 3D Solver to support the next generation of electronic designs, focusing on its advanced algorithms, robust architecture, and scalability. By utilizing the high computational capacity of Clarity 3D Solver, engineers and designers can achieve unprecedented levels of precision and performance, foster innovation, and optimize complex electronic systems. The integration of Clarity 3D Solver into electronic design workflows is set to transform the industry, enabling faster development cycles, improved functionality, and superior optimization results.

As 3D-IC technology advances to mitigate the slowing of Moore's law and accommodate the demands of high performance and compact designs, an efficient and accurate numerical solution for mechanical reliability challenges in 3DIC designs is becoming increasingly critical. However, the massive dimensions of the design model, coupled with the broad spectrum of design scales and the presence of minuscule critical mechanical features, collectively present substantial numerical analysis obstacles in mechanical modeling and stress simulation of 3DIC. This paper presents an innovative mechanical warpage and stress solver, focusing on optimizing thermal and mechanical design for 3DIC, such as CoWoS-L, HBM, among others.

Our methodology employs both TSMC 3Dblox™ and Samsung 3DCODE platforms to leverage their advanced 3D-IC design capabilities in improving design efficiency, and an automated multi-level modeling integrated with adaptive mesh for the efficient and accurate stress and reliability analysis. As a further advantage, AI is incorporated to enable robust chip mechanical modeling from detailed GDS designs and mechanical design optimization. Our simulation framework is validated against experimental data as well as golden references by foundries and customers, demonstrating its effectiveness in addressing the numerical challenges. The simulation results display detailed warpage distribution across the design and identify the stress results at critical spots, including through-silicon via (TSV), solder balls and microbumps. With our cutting-edge mechanical stress simulation approach, designers gain in-depth knowledge of the 3DIC mechanical design, empowering them to enhance design reliability and efficiency.

In the rapidly evolving world of electronic systems, the need for integrated simulation solutions is at an all-time high. "Integrated Intelligence: Exploring Cadence’s Comprehensive Multiphysics Simulation Solutions" explores how Cadence’s suite of tools combines multiple domains—electromagnetic, thermal, and mechanical—to enable comprehensive, system-level analysis. This presentation will demonstrate how the seamless integration of these multiphysics solvers speeds up design verification, enhances collaboration across engineering disciplines, and increases overall design reliability. By leveraging intelligent automation and unified data models, engineers can predict real-world performance with greater speed and confidence. Attendees will learn how Cadence’s innovative solutions are transforming electronic design workflows and opening the way for the next generation of optimized, robust products.

EM analysis has long been a critical technology in the development of RF components to provide insight into how physical design impacts electrical performance. The demands on EM technology are evolving as products move higher in frequency, adopt greater levels of integration and miniaturization, thereby increasing the electrical size of the analysis and the likelihood of parasitic behavior that will affect performance. This presentation looks at the design trends driving the need for fast and accurate EM technology utilizing massive parallelization to address the larger analysis challenges posed by today’s RF systems. Furthermore, the talk presents how the Clarity 3D FEM solver has been integrated within the Microwave Office design software to provide in-situ EM analysis of complex RF structures such as MMICs and RF PCBs.

This presentation covers how various companies in the EDA and Systems space are accelerating their chip design by leveraging Cadence tools in the cloud, from front-end to back-end workflows including emulation in the Cloud. Many companies from start-ups to large companies globally are accelerating innovation, engineering productivity and time to tape out using the scalability and flexibility offered by the Cloud, and this presentation will cover some examples from the industry. We’ll also cover the current advances and challenges for cloud migration including aspects of security in the cloud. Finally, the presentation will touch upon how customers can take advantage of the latest AI/ML enabled Cadence tools in the cloud and how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. You’ll learn how to harness the full potential of cloud technology to streamline your EDA workflows and accelerate innovation. 

The semiconductor industry is undergoing a major transformation from traditional monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This shift aims to mitigate the complexities associated with scaling designs, optimizing yields, and addressing rising fabrication costs. Economic drivers, such as increasing transistor costs and diminishing returns from Moore’s Law, are fueling this transition. To navigate this change, the industry needs advanced solutions that address a wide range of system requirements and facilitate efficient design through integrated architecture, tools, flows, and system IP.

In this presentation, discover how to expedite your physical AI, including automotive and, SoC designs, with Cadence’s advanced chiplet-based platform. The industry is currently witnessing the convergence of two seemingly opposing trends: the move towards high-performance, centralized computation (e.g., enabling software-defined vehicles) and the disaggregation of computation into discrete chiplets that can be independently verified and certified. Cadence’s multi-chiplet-based architecture addresses both demands by incorporating high-performance compute chiplets and ensuring multi-die interoperability. In this presentation, we will unveil our Physical AI Chiplet platform in design, including a framework for system and safety management, addressing the needs of a multitude of physical AI designs, including automotive advanced driver-assistance systems (ADAS), drones, and robotics applications.

As semiconductor leaders shift toward chiplet-based architectures to maximize flexibility, performance, and cost efficiency, new security challenges emerge at both the physical and system levels. This presentation introduces Secure-IC’s comprehensive approach to securing modular SoCs — from the earliest design stages to in-field operation.

We will explore how Secure-IC enables trusted communication between heterogeneous chiplets using lightweight hardware IPs and cryptographic protocols, including MACsec and Post-Quantum cryptography (PQC). A special focus will be given to integration strategies across die-to-die interfaces and multi-vendor packaging scenarios.

Beyond IP blocks, we will demonstrate how security is verified during RTL development using Secure-IC’s Virtualyzr™ and Catalyzr™ tools, enabling simulation of threat scenarios and attack injection within standard Cadence verification flows. We will also highlight how the Securyzr™ lifecycle management platform provides monitoring, updates, and security orchestration throughout the product’s life — including PQC-based secure updates.

With increasing SoC complexity, the integration of high-speed memory and interface IP is crucial for achieving performance and power efficiency targets. This presentation highlights Cadence’s integrated design methodology for LPDDR and PCIe Gen6 IP, addressing the growing need for bandwidth, low latency, and design scalability in next-generation SoCs. By tightly coupling LPDDR PHY and controller IP with PCIe Gen6 interface IP in a unified design and verification environment, Cadence enables early architecture exploration, protocol compliance, and rapid convergence on PPA goals. The solution supports automated configuration, silicon-proven interoperability, and advanced co-optimization techniques. Real-world case studies will demonstrate how this approach reduces integration effort, accelerates time-to-market, and ensures robust performance in AI, mobile, and high-performance computing applications.

With the rise of Agentic and Generative AI, datacenter architectures are evolving into AI-centric clouds and compute factories, driving a major shift across the computing landscape. This momentum in HPC and AI is fueling demand for advanced SoC, chip-to-chip, and modular architectures tailored to these emerging workloads. As performance and compute needs escalate, standards bodies and IP providers are responding with scalable solutions for xPU designs. This session explores critical memory standards such as the latest LPDDR and HBM, along with key interfaces such as 112G/224G, UALink, Ultra Ethernet, PCIe, and CXL—as well as chiplet and die-to-die technologies like UCIe, which are foundational to next-gen HPC and AI systems. Join us to explore the architectural demands of these platforms and how selecting the right IP can unlock design success.

We are a company dedicated to developing and continuously training AI-based speech signal processing models. Our proprietary algorithms include noise reduction, echo cancellation, howling suppression, beamforming, and, most recently, coneforming—an advanced algorithm that selects sound sources not only based on angle but also on distance information. We have implemented these algorithms on HiFi5, HiFi4, and HiFi Mini platforms, enabling deployment across a wide range of chipsets worldwide. Through this, we supply software for wireless earphones, hearing aids, headphones, walkie-talkies, in-vehicle audio systems, and voice-enabled home appliances, and will present how our solutions are applied in these products.  

For years, NPUs were positioned as the future of AI inference acceleration, promising high performance and low power. However, early implementations fell short, focusing narrowly on matrix multiplication and relying on CPUs to handle unsupported operations, which diluted their value and complicated integration.

That gap between promise and reality has quietly closed. Today’s NPUs like the Cadence Neo NPU offer near-complete operator coverage and robust vector offload, virtually eliminating fallback. When combined with the NeuroWeave SDK, developers gain access to complex compiler optimizations, including operator fusion, layer parallelization, and intelligent scheduling that unlock the NPU's full performance potential and low power.

This session will explore how modern NPUs are closing the gap between architectural promise and production reality, and why they’re becoming a must-have IP for any next-gen AI-enabled SoC.

This presentation covers how various companies in the EDA and Systems space are accelerating their chip design by leveraging Cadence tools in the cloud, from front-end to back-end workflows including emulation in the Cloud. Many companies from start-ups to large companies globally are accelerating innovation, engineering productivity and time to tape out using the scalability and flexibility offered by the Cloud, and this presentation will cover some examples from the industry. We’ll also cover the current advances and challenges for cloud migration including aspects of security in the cloud. Finally, the presentation will touch upon how customers can take advantage of the latest AI/ML enabled Cadence tools in the cloud and how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects. You’ll learn how to harness the full potential of cloud technology to streamline your EDA workflows and accelerate innovation.